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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4035B MSI 4-bit universal shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit universal shift register DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR). Each register is of a D-type master-slave flip-flop. Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. HEF4035B MSI When PE is LOW, data is shifted into the first register position from J and K and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and K = HIGH the first stage is in the hold mode. The outputs (O0 to O3) are either inverting or non-inverting, depending on T/C state. With T/C HIGH, O0 to O3 are non-inverting (active HIGH) and when T/C is LOW, O0 to O3 are inverting (active LOW). A HIGH on MR resets all four bit positions (O0 to O3 = LOW if T/C = HIGH, O0 to O3 = HIGH if T/C = LOW) independent of all other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Product specification Fig.2 Logic diagram. Philips Semiconductors 4-bit universal shift register HEF4035B MSI Philips Semiconductors Product specification 4-bit universal shift register HEF4035B MSI HEF4035BP(N): HEF4035BD(F): HEF4035BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.3 Pinning diagram. PINNING PE P0 to P3 J K CP T/C MR O0 to O3 parallel enable input parallel data inputs first stage J-input (active HIGH) first stage K-input (active LOW) clock input (LOW to HIGH edge-triggered) true/complement input master reset input buffered parallel outputs FUNCTION TABLES Serial operation first stage INPUTS CP J H L H L X Note 1. T/C = HIGH; PE = LOW X K H L L H X MR L L L L H OUTPUT O0 + 1 H L O0 O0 L MODE OF OPERATION D flip-flop D flip-flop toggle no change reset Notes 1. T/C = HIGH; PE = HIGH; MR = LOW = positive-going transition H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Parallel operation INPUTS CP P0 H L P1 H L P2 H L P3 H L O0 H L O1 H L O2 H L O3 H L OUTPUTS January 1995 4 Philips Semiconductors Product specification 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH MR On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH T/C On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 170 70 50 150 65 50 115 50 40 115 50 40 105 50 35 85 45 35 60 30 20 60 30 20 340 140 100 300 130 100 230 100 80 230 100 80 210 100 70 170 90 70 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF4035B MSI TYPICAL EXTRAPOLATION FORMULA 143 ns + (0,55 ns/pF) CL 59 ns 42 ns 54 ns 42 ns 88 ns 39 ns 32 ns 88 ns 39 ns 32 ns 78 ns 39 ns 27 ns 58 ns 34 ns 27 ns 10 ns 9 ns 6 ns 10 ns 9 ns 6 ns + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (0,55 ns/pF) CL + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (0,55 ns/pF) CL + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (0,55 ns/pF) CL + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (0,55 ns/pF) CL + (0,23 ns/pF) CL + (0,16 ns/pF) CL + (1,0 ns/pF) CL + (0,42 ns/pF) CL + (0,28 ns/pF) CL + (1,0 ns/pF) CL + (0,42 ns/pF) CL + (0,28 ns/pF) CL 123 ns + (0,55 ns/pF) CL January 1995 5 Philips Semiconductors Product specification 4-bit universal shift register HEF4035B MSI TYPICAL EXTRAPOLATION FORMULA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Figs 4 and 5 VDD V Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Set-up times Pn CP 5 10 15 5 10 15 5 10 15 5 10 15 5 PE CP 10 15 5 J, K CP Hold times Pn CP 10 15 5 10 15 5 PE CP 10 15 5 J, K CP Maximum clock pulse frequency 10 15 5 10 15 SYMBOL MIN. TYP. MAX. 80 tWCPL 40 30 50 tWMRH 30 20 50 tRMR 40 25 40 tsu 25 15 50 tsu 35 30 55 tsu 35 25 25 thold 20 20 15 thold 10 5 10 thold 10 10 5 fmax 12 15 40 20 15 25 15 10 20 15 10 5 0 0 25 15 10 40 15 10 10 10 10 -5 -5 -5 -5 0 0 10 25 30 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1 000 fi + (foCL) x VDD 2 6 000 fi + (foCL) x VDD 20 000 fi + (foCL) x VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 7 Product specification Fig.4 Waveforms showing minimum clock pulse width, set-up times, hold times. Set-up times and hold times are shown as positive values but may be specified as negative values. Philips Semiconductors 4-bit universal shift register HEF4035B MSI Philips Semiconductors Product specification 4-bit universal shift register HEF4035B MSI APPLICATION INFORMATION Some examples of applications for the HEF4035B are: * Counters, registers, arithmetic-unit registers, shift-left/shift-right registers. * Serial-to-parallel/parallel-to-serial conversions. * Sequence generation. * Control circuits. * Code conversion. Fig.5 Waveforms showing minimum MR pulse width and MR recovery time. Fig.6 Shift-left/shift-right register. January 1995 8 |
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